a) Field of the Invention
The present invention relates to a multiplexer for selectively outputting input signals, and more particularly to a differential multiplexer for selecting an input signal in response to a pair of differential clocks and outputting a pair of differential signals, and to a differential logic circuit using such a differential multiplexer.
b) Description of the Related Art
Some of conventional audio and video apparatuses have analog input/output terminals. Audio and video signals are transferred in analog forms to and from these apparatuses. Analog communications are now being replaced by digital communications. Of various digital communications, IEEE 1394 digital serial communications have drawn attention.
FIG. 2 shows a configuration of a communication network of IEEE 1394.
For example, this network has five nodes (communication apparatuses) ND1 to ND5 connected by cables BS. In the following, all the nodes are called collectively as a node ND or each node is also called a node ND. Each node ND has a node ID (identifier). For example, the node ND1 has an identifier of "1", the node ND2 has an identifier of "2", the node ND3 has an identifier of "3", the node ND4 has an identifier of "4", and the node ND5 has an identifier of "5". Of these nodes, the node having a largest node ID is a root node. In this example, the node ND5 is the root node.
FIG. 3 shows the structure of one node ND.
A node ND has an IEEE 1394 interface 1 and a device 4. The device 4 is, for example, an audio apparatus, a video apparatus, a computer, or the like. The IEEE 1394 interface 1 is constituted of a combination of a link layer (semiconductor chip) 2 and a physical layer (semiconductor chip) 3. The physical layer 3 transfers a signal directly to and from a cable BS, and the link layer 2 transfers a signal to and from the device 4.
The cable BS has two sets of twisted pair. One set of twisted pair transfers a pair of differential data signals Data and -Data having opposite phases. The other set of twisted pair transfers a pair of differential strobe signals Strobe and -Strobe having opposite phases. The strobe signal Strobe is a DS encoded signal of the data signal Data. The details will be later described with reference to FIG. 4.
A signal rate of the fours signals propagating on the cable BS is any one of the three rates selected from 98.304 Mbits/sec (hereinafter represented by 100 Mbps for convenience), 196.608 Mbits/sec (also 200 Mbps), and 393.216 Mbits/sec (also 400 Mbps).
The physical layer 3 is required to have an internal clock of 100 MHz if the serial data Data is transmitted at 100 Mbps, an internal clock of 200 MHz if transmitted at 200 Mbps, or an internal clock of 400 MHz if transmitted at 400 Mbps.
Data T.times.D is transferred between the link layer 2 and physical layer 3 always at 49.152 MHz (hereinafter represented by 50 Mbps for convenience) irrespective of the signal rate selected. The data T.times.D corresponds to parallel data of serial-parallel converted serial data Data. The data T.times.D is a parallel signal of 400/50 Mbps=8 bits if the serial data Data has a signal rate of 400 Mbps, a parallel signal of 200/50 Mbps=4 bits if a signal rate of 200 Mbps, or a parallel signal of 100/50 Mbps=2 bits if a signal rate of 100 Mbps. It is assumed in the following description that the serial data Data is transferred at 400 Mbps.
FIG. 4 shows the circuit structure of a conventional physical layer 3, and FIG. 6 is a timing chart illustrating the operation of the circuit. In the following description, it is assumed that the physical layer 3 transmits the signals Data, -Data, Strobe, and -Strobe over the cable BS.
The physical layer 3 parallel-serial converts input 8-bit parallel data T.times.D[0] to T.times.D[7] and outputs pairs of differential data signals Data and -Data, as well as pairs of differential strobe signals Strobe and -Strobe. The strobe signals Strobe and -Strobe are signals obtained by DS encoding the data signals Data and -Data, and are transmitted in place of clocks signals (e.g., 400 MHz). A partner physical layer receives the data signals Data and -Data and strobe signals Strobe and -Strobe, and reproduces clock signals by decoding the data and strobe signals. The IEEE 1394 specification stipulates that the physical layer transmits the fours signals Data, -Data, Strobe, and -Strobe over the cable BS.
Eight selectors SEL0 to SEL7 and eight D-type flip-flops FF0 to FF7 are respectively (alternately) and serially connected to constitute a well-known parallel-serial converter circuit. This parallel-serial converter circuit converts 8-bit parallel data T.times.D[0] to T.times.D[7] into serial data N1.
The 8-bit parallel data T.times.D[0] to T.times.D[7] is input to first input terminals of the eight selectors SEL0 to SEL7. The eight selectors SEL0 to SEL7 select and output signals on the first input terminals while a select signal Mux_sel takes a high level, and select and output signals on second input terminals while the select signal Mux_Sel takes a low level. The D-type flip-flops FF0 to FF7 hold and output input signals D as output signals Q in response to a positive (rise) edge of a clock Clk1.
The 8-bit data T.times.D[0] to T.times.D[7] is actually transferred via eight parallel signal lines. In FIG. 5, the 8-bit data T.times.D[0] to T.times.D[7] is shown collectively for simplicity. The data T.times.D[0] to T.times.D[7] has a signal rate of 50 Mbps, signals D0 to D7 are transferred during a first cycle, and signals D8 to D15 are transferred during a second cycle. For example, during the first cycle, signals T.times.D[0]=D0, T.times.D[1]=D1, T.times.D[2]=D2, T.times.D[3]=D3, T.times.D[4]=D4, T.times.D[5]=D5, T.times.D[6]=D6, and T.times.D[7]=D7 are transferred.
Clocks Clk1 and Clk2 have a clock frequency of 400 MHz (2.5 ns period). The select signal Mux_Sel has a frequency of 50 MHz (20 ns period). A signal enc has a frequency of 200 MHz (5 ns period).
As shown in FIG. 5, when the select signal Mux_Sel takes the high level, the selector SEL0 selects the data D0 (T.times.D[0]) at the first input terminal and outputs it to an input terminal D of the flip-flop FF0, and the selector SEL1 selects the data D1 (T.times.D[1]) at the first input terminal and outputs it to an input terminal D of the flip-flop FF1. Similarly, the selectors SEL2 to SEL7 select data D2 to D7 and output them to input terminals D of the flip-flops FF2 to FF7.
Thereafter, when the clock Clk1 rises, the flip-flop FF0 outputs the data D0 at the input terminal D as serial data N1, and the flip-flop FF1 outputs the data D1 at the input terminal D as an output signal Q. Similarly, the flip-flops FF2 to FF7 output the data D2 to D7 as output signals Q which are applied to the second input terminals of the preceding selectors SEL1 to SEL6.
Next, when the select signal Mux_Sel takes the low level, the selector SEL0 selects the data D1 (T.times.D[1]) at the second input terminal and outputs it to the input terminal D of the flip-flop FF0, and the selector SEL1 selects the data D2 (T.times.D[2]) at the second input terminal and outputs it to the input terminal D of the flip-flop FF1. Similarly, the selectors SEL2 to SEL6 select data D3 to D7 and output them to the input terminals D of the flip-flops FF2 to FF6. The selector SEL7 selects a ground signal gnd and outputs it to the input terminal D of the flip-flop FF7.
Thereafter, when the clock Clk1 rises, the flip-flop FF0 outputs the data D1 at the input terminal D as the serial data N1, and the flip-flop FF1 outputs the data D2 at the input terminal D as the output signal Q which is applied to the second input terminal of the selector SEL0. Similarly, the flip-flops FF2 to FF7 output the data D3 to D7 as output signals Q which are applied to the second input terminals of the preceding selectors SEL1 to SEL5. The flip-flop FF7 outputs the ground signal gnd as the output signal Q which is supplied to the second input terminal of the preceding selector SEL6.
Operations similar to the above are repeated to sequentially output D0 to D7 as the serial data N1, and thereafter D8 to D15 are sequentially output.
An exclusive logical sum (XOR) circuit 10 calculates a logical sum of the serial data N1 and signal enc to output a strobe signal N2 of the strobe signal Strobe.
The strobe signal N2 is delayed from the serial data N1 by a process time of the XOR circuit 10. In order to synchronize the signals N1,N2 and the like, D-type flip-flops FF11 to FF14 are provided.
The D-type flip-flops FF11 to FF14 output signals at the input terminals D from the output terminals Q in response to a positive edge of the clock Clk2. The flip-flop FF11 outputs the data N1 input to the input terminal D from the output terminal Q as the data signal Data. The flip-flop FF12 outputs the inverted data N1 input to the input terminal D from the output terminal Q as the paired differential data signal -Data. The flip-flop FF13 outputs a strobe signal N2 input to the input terminal D from the output terminal Q as the strobe signal Strobe. The flip-flop FF14 outputs the inverted strobe signal N2 input to the input terminal D from the output terminal Q as the paired differential strobe signal -Strobe. All the data signals Data and -Data and strobe signals Strobe and -Strobe are transmitted at 400 Mbps synchronously with the clock Clk2.
The 8-bit parallel data T.times.D[0] to T.times.D[7] has the signal rate of 50 Mbps. The serial data signals Data and -Data and strobe signals Strobe and -Strobe have the signal rate of 400 Mbps (=50 Mbps.times.8 bits).
The clock Clk1 of 400 MHz (2.5 ns period) becomes necessary for parallel-serial conversion, and the clock Clk2 of 400 MHz (2.5 ns period) becomes necessary for synchronization among the output signals Data, -Data, Strobe, and -Strobe.
Namely, in order to transmit four output signals at 400 Mbps, the clocks Clk1 and Clk2 of 400 MHz are required.
According to the IEEE 1394 specifications, any signal rate can be selected from 100 Mbps, 200 Mbps, and 400 Mbps. Presently, IEEE 1394 interfaces compatible with the signal rate of 100 Mbps and 200 Mbps are mainly used. It is sufficient if clocks of 200 MHz are supplied to the physical layer in this interface, and clocks of 400 MHz are not necessary.
However, IEEE 1394 interfaces compatible with the signal rate of 400 Mbps are under development. The physical layer of this interface requires the clocks Clk1 and Clk2 of 400 MHz as described above.
As compared to 200 Mbps compatible IEEE 1394 interfaces, the 400 Mbps compatible interfaces require clocks of higher frequency. In order to use clocks of higher frequency, more sophisticated semiconductor process technologies are required to realize high speed operation and high precision alignment, so that the manufacturing cost of physical layers increases. As the clock frequency is doubled, the power consumption is also doubled.
Markets desire 400 Mbps compatible physical layer semiconductor chips which can suppress the power consumption to the same degree as 200 Mbps compatible physical layer semiconductor chips. However, this market needs cannot be satisfied as yet because it is difficult to halve the power consumption.
If the power source voltage is lowered, the power consumption can be lowered. However, if the power source voltage is lowered, a stable operation cannot be expected.
Another problem is that pairs of differential data signals Data and -Data and differential strobe signals Strobe and -Strobe to be output from the physical layer are likely to have time delays jitters).